1. Technical Field
The present invention generally relates to a semiconductor memory device and, more particularly, to a non-volatile semiconductor memory device.
2. Background Art
Among various kinds of semiconductor memory devices, a FeRAM (a ferroelectric memory) has memory cells, in each of which a gate electrode 21A and a source region 22A of, for example, an N-channel type MIS transistor are electrically connected to a word line WL and a bit line BL, respectively, and a ferroelectric capacitor 30A is electrically connected between a drain region 23A and a plate line PL of this MIS transistor, as is seen from FIG. 10(A) showing an equivalent circuit thereof.
In the case of such a kind of a semiconductor memory device 1A, when one of binary data xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d, for instance, data xe2x80x9c1xe2x80x9d is written to a memory cell 10A, the word line WL is set at a high level (H) in a state in which the bit line BL is maintained at the high level (H), while the plate line PL is maintained at a low level (L). Consequently, the MIS transistor 10A is put into an on-state. Thus, in the ferroelectric capacitor 30A, an electrode 31A electrically connected to the drain region 23A of the MIS transistor 10A is set at the high level (H), while an electrode 32A electrically connected to the plate line PL thereof is set at the low level (L), as illustrated in FIG. 10(B). This results in occurrence of polarization in a ferroelectric layer of the ferroelectric capacitor 30A.
In contrast with this, when data xe2x80x9c0xe2x80x9d is written to the memory cell 10A (that is, when deleting data written thereto), the word line WL is set at the high level (H) in a state in which the bit line BL is maintained at the low level (L) and the plate line PL is set at the high level (H), as illustrated in FIG. 11(A). Consequently, the MIS transistor 10A is brought into an on-state. In the ferroelectric capacitor 30A, an electrode 31A electrically connected to the drain region 23A of the MIS transistor 10A is set at the low level (L), while an electrode 32A electrically connected to the plate line PL is set at the high level (H), as illustrated in FIG. 11(B). Thus, the ferroelectric layer of the ferroelectric capacitor 30A is polarized in a direction opposite to the direction of polarization in the case of writing the data xe2x80x9c1xe2x80x9d thereto.
Next, an operation of reading information is described hereinbelow. First, the bit line BL is precharged at ground potential. Thereafter, the bit line BL is put in a high impedance state. Subsequently, the electric potential of the plate line PL is fixed at ground potential. At that time, the ferroelectric capacitor 30A is maintained in the polarized state as before. Then, the plate line PL is set at the high level (H). At that time, charges are discharged from the ferroelectric capacitor 30A. The amount of the discharged charge varies with a direction in which the polarization is previously caused. Moreover, the discharged electric charge appears as a voltage of the bit line BL. Thus, it is determined by amplifying this voltage by means of a sense amplifier which ofxe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d the data represents.
However, in the case of the conventional FeRAM, when information is read, the ferroelectric capacitor 30A discharges. Thus, it is necessary for holding the data to write the data thereto again. That is, in the case of the conventional FeRAM, a destructive read operation is performed. Meanwhile, generally, in the case of FeRAMs, the number of times of writing data is limited. Therefore, in the case of the destructive read operation, the writing of data is needed every time information is read. Consequently, the scope of applications of the conventional FeRAM is extremely limited.
Thus, problems to be solved by the present invention reside in constituting a memory cell from one transistor and one capacitor and in providing a non-volatile semiconductor memory device that can read data nondestructively.
To solve the foregoing problems, according to a first aspect of the present invention, there is provided a semiconductor memory device, which first, comprises at least a plurality of memory cells each formed by stacking a plate electrode, a ferroelectric layer, an insulating film, a channel region of a MIS (Metal Insulator Semiconductor) transistor, a gate insulating film of the MIS, and a gate electrode of the MIS transistor in this order. A word line is electrically connected to the gate electrode of each of the plurality of memory cells. First and second bit lines are electrically connected to a source region and a drain region of the MIS transistor, respectively. A plate line is electrically connected to the plate electrode.
In the specification of the present application, the term xe2x80x9cMISxe2x80x9d is strictly for the purpose of representing a structure and does not mean that the gate electrode is limited to a metallic one. The term xe2x80x9cMISxe2x80x9d implies that, for example, a doped silicon film may be used as the gate electrode.
According to the first aspect of the present invention, the MIS transistor is, for instance, a thin film transistor.
In the semiconductor memory device of the present invention, when data is stored in the memory cell, a voltage of a polarity corresponding to the data is applied between the plate line and each of the first and second bit lines. Moreover, a gate voltage for turning on the MIS transistor is applied to the gate electrode from the word line.
For example, when one kind of binary data is stored in the memory cell, a voltage of a polarity corresponding to the one kind of binary data is applied between the plate line and each of the first and second bit lines. Moreover, a gate voltage for turning on the MIS transistor is applied to the gate electrode from the word line. In contrast, when the other kind of binary data is stored in the memory cell, a voltage of a polarity opposite to the polarity of the voltage applied in the case of storing the one kind of data is applied between the plate line and each of the first and second bit lines. Moreover, a gate voltage for turning on the MIS transistor is applied to the gate electrode from the word line.
When data is written thereto in this manner, electric charges corresponding to the polarity of the voltage applied between the plate line and each of the first and second bits are stored in the ferroelectric layer.
In the semiconductor memory device constructed in this way, the channel region of the MIS transistor is affected in a manner varying according to the polarity of the polarized ferroelectric layer by the charges stored in the ferroelectric layer. This results in change in the source-drain-current-gate-voltage characteristic of the MIS transistor. Thus, let xe2x80x9ca first gate voltagexe2x80x9d represent a gate voltage, at which the source-drain current reaches a predetermined level according to the source-drain-current-gate-voltage characteristic of the MIS transistor, when one kind of binary data xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d is written thereto. Further, let xe2x80x9ca second gate voltagexe2x80x9d represent a gate voltage, at which the source-drain current reaches a predetermined value, when the other kind of binary data xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d is written thereto. Moreover, let xe2x80x9ca data reading gate voltagexe2x80x9d represent an electric potential level between the first and second gate voltages. When a reading voltage is applied between the source and the drain of the MIS transistor while the data reading gate voltage is applied to the gate electrode from the word line, it is detected from the first bit line or the second bit line whether or not a source-drain current flows. Consequently, it is decided which kind of the data xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d is written thereto.
When data is read in this way, the charges stored in the ferroelectric layer merely electrostatically affect the channel region and are not discharged in the semiconductor memory device according to the present invention. Therefore, even when the data written to the memory cells are read, the electric charges having been stored in the ferroelectric layer remain still stored therein. Consequently, the data is not destroyed.
It has been known for some time that ferroelectric materials exhibit internal polarization and that this can be adapted to provide two stable polarization states. Switching between the two states can be used for storage of binary data. Although memory devices have been implemented using this technique there has been the problem that the data read operation is destructive of the data. That is, to distinguish between the two possible polarization states requires the application of a voltage sufficient to switch between the two states. The data is thus lost upon reading. To overcome this problem it is possible to re-write the data after reading but this obviously incurs an undesirable overhead in terms of circuit components, power consumption and speed of operation. These factors undesirably influence overall device size, ease of fabrication and cost. In addition, increases in storage density require a corresponding decrease in read current, which has an adverse effect upon read sensitivity.
A proposal for mitigating the above mentioned disadvantages is to use a thin film transistor structure in which a ferroelectric material is used as the gate insulator. The basic structure of such a device is illustrated in FIG. 12. A layer of ferroelectric material (PZT) is provided over the conventional source (S), channel (C) and drain (D) active layer so as to separate the gate (G) therefrom. That is, the ferroelectric material acts as the gate dielectric. The ferroelectric material causes a shift in threshold voltage of the transistor wherein the shift is dependent upon the state of polarization of the ferroelectric material. In other words, the result is the introduction of a hysterisis in the transfer characteristics of the transistor. The hysterisis in the transfer characteristic can be detected without changing the state of polarization of the ferroelectric material. Non-destructive reading of the stored data can thus be achieved. Moreover, it is found that device sensitivity remains constant with changes in the W/L dimensions of the transistor.
From the foregoing description it will be appreciated that the structure according to FIG. 12 has very significant potential benefits. However, attempts at implementation of the structure in practical memory devices have encountered two key problems. Firstly, difficulties have been encountered in the physical interface between the ferroelectric material and silicon used for the active source/channel/drain layer. Although this problem can be mitigated to some extent by the introduction of buffer layers, such buffer layers are difficult to fabricate and they significantly degrade the performance of the device. Secondly, and more importantly, when the structure is repeated in a matrix to form a large scale memory device it is found to be exceptionally prone to cross-talk, ie the write operation for one cell often affects other cells.
Against this background, in one aspect of the present invention it has been recognised that because the active layer is very thin (typically of the order of 50 Angstroms), charges on the back of the channel affect the threshold voltage of the transistor. The effect is significant, with a shift of xc2x11 volt in the threshold voltage being caused by a charge of the order of xc2x11.6xc3x9710xe2x88x927 coulomb. The said one aspect of the present invention uses this normally undesirable characteristic in order to mitigate the problems in practical implementation of a memory device comprising a thin film structure and ferroelectric data storage.
According to one aspect of the present invention there is provided a semiconductor memory device comprising: an active layer in which are formed a transistor source, channel and drain; a gate for the transistor; a layer of ferroelectric material; and an electrode for applying a voltage to the ferroelectric material; the electrode being spaced apart from the gate, the layer of ferroelectric material having two stable states of internal polarization, and the arrangement being such that the two states of polarization have a detectable difference in effect upon the transfer characteristic of the transistor.